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D N EW (R) FOR 5108 L D ED MEN 106, E C O M E E EL5 RE S NOT Data Sheet
ESIG
NS
EL5197, EL5197A
May 16, 2007 FN7184.2
Single 200MHz Fixed Gain Amplifier with Enable
The EL5197 and EL5197A are fixed gain amplifiers with a bandwidth of 200MHz, making these amplifiers ideal for today's high speed video and monitor applications. These amplifiers feature internal gain setting resistors and can be configured in a gain of +1, -1 or +2. The same bandwidth is seen in both gain-of-1 and gain-of-2 applications. With a supply current of just 4mA and the ability to run from a single supply voltage from 5V to 10V, these amplifiers are also ideal for hand held, portable or battery powered equipment. The EL5197A also incorporates an enable and disable function to reduce the supply current to 100A typical per amplifier. Allowing the CE pin to float or applying a low logic level will enable the amplifier. The EL5197 is offered in the 5 Ld SOT-23 package and the EL5197A is available in the 6 Ld SOT-23 as well as the industry-standard 8 Ld SOIC packages. Both operate over the industrial temperature range of -40C to +85C.
Features
* Gain selectable (+1, -1, +2) * 200MHz -3dB BW (AV = 1, 2) * 4mA supply current * Fast enable/disable (EL5197A only) * Single and dual supply operation, from 5V to 10V or 2.5V to 5V * Available in SOT-23 packages * Triple (EL5397) available * 400MHz, 9mA products available (EL5197 and EL5396) * Pb-Free plus anneal available (RoHS compliant)
Applications
* Battery powered equipment * Hand held, portable devices * Video amplifiers * Cable drivers * RGB amplifiers * Test equipment * Instrumentation * Current to voltage converters
Pinouts
EL5197A (8 LD SOIC) TOP VIEW
NC 1 IN- 2 IN+ 3 VS- 4 + 8 CE 7 VS+ 6 OUT 5 NC
EL5197A (6 LD SOT-23) TOP VIEW
OUT 1 VS- 2 IN+ 3 6 VS+ 5 CE 4 INOUT 1 VS- 2 IN+ 3
EL5197 (5 LD SOT-23) TOP VIEW
5 VS+
+-
+4 IN-
.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5197, EL5197A Ordering Information
PART NUMBER EL5197CW-T7 EL5197CW-T7A EL5197ACW-T7 EL5197ACS EL5197ACS-T7 EL5197ACS-T13 EL5197ACSZ (Note) EL5197ACSZ-T7 (Note) EL5197ACSZ-T13 (Note) S S S 5197ACS 5197ACS 5197ACS 5197ACS Z 5197ACS Z 5197ACS Z PART MARKING TAPE & REEL 7" (3k pcs) 7" (250 pcs) 7" 7" 13" 7" 13" 5 Ld SOT-23 5 Ld SOT-23 6 Ld SOT-23 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) PACKAGE PKG. DWG. # MDP0038 MDP0038 MDP0038 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN7184.2 May 16, 2007
EL5197, EL5197A
Absolute Maximum Ratings (TA = +25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . . . 11V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V
Thermal Information
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Operating Ambient Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER AC PERFORMANCE BW
VS+ = +5V, VS- = -5V, RL = 150, TA = +25C unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT
-3dB Bandwidth
AV = +1 AV = -1 AV = +2
200 200 200 20
MHz MHz MHz MHz V/s ns nV/Hz pA/Hz pA/Hz %
BW1 SR tS eN iNiN+ dG dP DC PERFORMANCE VOS TCVOS AE RF, RG
0.1dB Bandwidth Slew Rate 0.1% Settling Time Input Voltage Noise IN- Input Current Noise IN+ Input Current Noise Differential Gain Error (Note 1) AV = +2 VO = -2.5V to +2.5V, AV = +2 VOUT = -2.5V to +2.5V, AV = -1 1800
2200 12 4.4 17 50 0.03 0.04
Differential Phase Error (Note 1) AV = +2
Offset Voltage Input Offset Voltage Temperature Coefficient Gain Error Internal RF and RG Measured from TMIN to TMAX VO = -3V to +3V
-10
1 5
10
mV V/C
-2 320
1.3 400
2 480
%
INPUT CHARACTERISTICS CMIR +IIN -IIN RIN CIN Common Mode Input Range + Input Current - Input Current Input Resistance Input Capacitance at IN+ 3V -60 -30 3.3V 1 1 45 0.5 60 30 V A A k pF
OUTPUT CHARACTERISTICS VO Output Voltage Swing RL = 150 to GND RL = 1k to GND IOUT SUPPLY ISON ISOFF Supply Current - Enabled Supply Current - Disabled No load, VIN = 0V No load, VIN = 0V 3 4 100 5 150 mA A Output Current RL = 10 to GND 3.4V 3.8V 95 3.7V 4.0V 120 V V mA
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FN7184.2 May 16, 2007
EL5197, EL5197A
Electrical Specifications
PARAMETER PSRR -IPSR VS+ = +5V, VS- = -5V, RL = 150, TA = +25C unless otherwise specified. (Continued) DESCRIPTION Power Supply Rejection Ratio - Input Current Power Supply Rejection CONDITIONS DC, VS = 4.75V to 5.25V DC, VS = 4.75V to 5.25V MIN 55 -2 TYP 75 2 MAX UNIT dB A/V
ENABLE (EL5197A ONLY) tEN tDIS IIHCE IILCE VIHCE VILCE NOTES: 1. Standard NTSC test, AC signal amplitude = 286mVP-P, f = 3.58MHz 2. Measured from the application of CE logic until the output voltage is at the 50% point between initial and final values Enable Time Disable Time (Note 2) CE Pin Input High Current CE Pin Input Low Current CE Input High Voltage for Disable CE Input Low Voltage for Enable CE = VS+ CE = VSVS+ -1 VS+ -3 40 600 0.8 0 6 -0.1 ns ns A A V V
4
FN7184.2 May 16, 2007
EL5197, EL5197A Typical Performance Curves
Frequency Response (Gain) 6 Normalized Magnitude (dB) AV = -1 2 -2 -6 -10 -14 1M RL = 150 10M 100M 1G AV = 2 0 -90 -180 -270 90
Frequency Response (Phase), All Gains
AV = 1
Phase ()
-360 1M
RL = 150 10M 100M 1G
Frequency (Hz) Frequency Response for Various CL 14 Normalized Magnitude (dB) 10 6 10pF added 2 -2 -6 1M 0pF added 0.5 0 1M RL = 150 AV = 2 RL = 150 22pF added Delay (ns) 3.5 3 2.5 2 1.5 1
Frequency (Hz) Group Delay vs Frequency
AV = 2
AV = 1
10M
100M
1G
10M
100M
1G
Frequency (Hz) Frequency Response for Various Common-Mode Input Voltages 3V 2 -2 -6 -10 -14 1M AV = 2 RL = 150 10M 100M 1G Magnitude () 0V -3V 1M
Frequency (Hz) Transimpedance (ROL) vs Frequency 10M Phase 0 -90 -180 10k ROL 1k -360 100 1k 10k 100k 1M 10M Frequency (Hz) 100M 1G -270 Phase () 100k
6 Normalized Magnitude (dB)
Frequency (Hz)
5
FN7184.2 May 16, 2007
EL5197, EL5197A Typical Performance Curves
(Continued)
PSRR and CMRR vs Frequency 20 0 PSRR/CMRR (dB) -20 -40 CMRR -60 -80 10k PSRR+ 250
-3dB Bandwidth vs Supply Voltage RL = 150
-3dB Bandwidth (MHz)
200 AV = 2
PSRR-
150
AV = -1
AV = 1
100k
1M
10M
100M
1G
100
5
6
7
8
9
10
Frequency (Hz)
Total Supply Voltage (V) -3dB Bandwidth vs Temperature 300
Peaking vs Supply Voltage 5 4 Peaking (dB) 3 AV = 2 2 1 0 RL = 150 5 6 7 8 9 10 AV = -1 AV = 1
250 -3dB Bandwidth (MHz) 200 150 100 50 0 -40 RL = 150 10 60 110 160
Total Supply Voltage (V) Peaking vs Temperature 1 0.8 Peaking (dB) 0.6 0.4 0.2 0 -40 RL = 150 10 60 110 160 1k
Ambient Temperature (C) Voltage and Current Noise vs Frequency
Voltage Noise (nV/Hz) Current Noise (pA/Hz)
100 iN10 eN
iN+
1 100
1k
Ambient Temperature (C)
10k 100k Frequency (Hz)
1M
10M
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FN7184.2 May 16, 2007
EL5197, EL5197A Typical Performance Curves
(Continued)
Closed Loop Output Impedance vs Frequency 100 10 1 0.1 0.01 0.001 100 Supply Current (mA) 10 8 6 4 2 0 1k 10k 1M 10M 100k Frequency (Hz) 100M 1G
Supply Current vs Supply Voltage
Output Impedance ()
0
2
4 6 8 Supply Voltage (V)
10
12
2nd and 3rd Harmonic Distortion vs Frequency -20 Harmonic Distortion (dBc) -30 -40 -50 -60 -70 -80 -90 1 10 Frequency (MHz) 100 2nd Order Distortion 3rd Order Distortion AV = +2 VOUT = 2VP-P RL = 100 25 Input Power Intercept (dBm) 20 15 10 5 0 -5
Two-Tone 3rd Order Input Referred Intermodulation Intercept (IIP3) AV = +2 RL = 150
-10 10
AV = +2 RL = 100 100 Frequency (MHz)
0.03 0.02 0.01 dG (%) or dP () 0 -0.01 -0.02 -0.03 -0.04
Differential Gain/Phase vs DC Input Voltage at 3.58MHz AV = 2 RL = 150 dP
0.04 0.03 0.02 dG (%) or dP ()
Differential Gain/Phase vs DC Input Voltage at 3.58MHz AV = 1 RL = 500
dP
dG
0.01 0 -0.01 -0.02 -0.03 dG
-0.05 -1
-0.5
0 DC Input Voltage (V)
0.5
1
-0.04 -1
-0.5
0 DC Input Voltage (V)
0.5
1
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FN7184.2 May 16, 2007
EL5197, EL5197A Typical Performance Curves
(Continued)
10 Output Voltage Swing (VPP) 8 6 4 2 0
Output Voltage Swing vs Frequency THD < 1% RL = 500
10 Output Voltage Swing (VPP) 8
Output Voltage Swing vs Frequency THD < 0.1%
RL = 150
RL = 500 6 RL = 150 4 2 0 AV = 2 1 10 Frequency (MHz) 100
AV = 2 1 10 Frequency (MHz) 100
Small Signal Step Response VS = 5V RL = 150 AV = 2
Large Signal Step Response VS = 5V RL = 150 AV = 2
200mV/div
1V/div
10ns/div
10ns/div
Settling Time vs Settling Accuracy 25 20 Settling Time (ns) 15 10 5 0 0.01 AV = 2 RL = 150 VSTEP = 5VP-P output 625
Transimpedance (RoI) vs Temperature
600 RoI (k)
575
550
0.1 Settling Accuracy (%)
1
525 -40
10
60 Die Temperature (C)
110
160
8
FN7184.2 May 16, 2007
EL5197, EL5197A Typical Performance Curves
(Continued)
6 Normalized Magnitude (dB) 2 -2 -6 -10
Frequency Response (Gain) SO8 Package AV = -1 AV = 2
90 0 -90 -180 -270
Frequency Response (Phase) SO8 Package
-14 1M
RL = 150 10M 100M 1G
Phase ()
AV = 1
-360 1M
RL = 150 10M 100M 1G
Frequency (Hz) PSRR and CMRR vs Temperature 90 80 ICMR/IPSR (A/V) 70 PSRR/CMRR (dB) 60 50 40 30 20 10 -40 10 60 Die Temperature (C) Offset Voltage vs Temperature 2 60 40 Input Current (A) 1 VOS (mV) 20 110 160 -0.5 -40 10 CMRR 1.5 PSRR 1 IPSR 0.5 0 ICMRICMR+ 2
Frequency (Hz) ICMR and IPSR vs Temperature
60 Die Temperature (C)
110
160
Input Current vs Temperature
IB0 -20 -40 IB+
0
-1
-2 -40
10
60 Die Temperature (C)
110
160
-60 -40
10
60 Die Temperature (C)
110
160
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FN7184.2 May 16, 2007
EL5197, EL5197A Typical Performance Curves
(Continued)
Positive Input Resistance vs Temperature 60 50 40 RIN+ (k) 30 20 10 0 -40 Supply Current (mA) 5 4 3 2 1
Supply Current vs Temperature
10
60 Die Temperature (C)
110
160
0 -40
10
60 Die Temperature (C)
110
160
4.2 4.1 4 VOUT (V) 3.9 3.8 3.7 3.6
Positive Output Swing vs Temperature for Various Loads -3.5 -3.6 1k -3.7 VOUT (V) -3.8 -3.9 -4 -4.1 10 60 Die Temperature (C) 110 160
Negative Output Swing vs Temperature for Various Loads 150
150
1k
3.5 -40
-4.2 -40
10
60 Die Temperature (C)
110
160
Output Current vs Temperature 130 4000
Slew Rate vs Temperature
Sink 125 IOUT (mA) Slew Rate (V/S) 3500
120
Source
3000
115 -40
10
60 Die Temperature (C)
110
160
2500 -40
AV = 2 RL = 150 10 60 Die Temperature (C) 110 160
10
FN7184.2 May 16, 2007
EL5197, EL5197A Typical Performance Curves
(Continued)
Enable Response
Disable Response
500mV/div
500mV/div
5V/div 5V/div
20ns/div
400ns/div
0.7 0.6 Power Dissipation (W) 0.5 0.4
Package Power Dissipation vs Ambient Temperature JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity Test Board 909mW
8 /W SO 0C 1 =1 JA
625mW
SO 8
SO T
391mW 0.3 0.2 0.1 0 -50-40 -25
-23 JA = 25 6 C/ W
Power Dissipation (W)
J
A
/W C 60 =1
435mW
J
A =2
SO T-2 30
3 W
C /
0
25
50
75 85 100
125
0 -50-40 -25
0
25
50
75 85 100
125
Ambient Temperature (C)
Ambient Temperature (C)
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FN7184.2 May 16, 2007
EL5197, EL5197A Pin Descriptions
8 Ld SOIC 1, 5 2 4 4 5 Ld SOT-23 6 Ld SOT-23 PIN NAME NC INFUNCTION Not connected Inverting input EQUIVALENT CIRCUIT
IN+
RG RF
IN-
Circuit 1
3 4 6
3 2 1
3 2 1
IN+ VSOUT
Non-inverting input Negative supply Output
(See circuit 1)
OUT RF
Circuit 2
7 8
5
6 5
VS+ CE
Positive supply Chip enable
VS+
CE
VSCircuit 3
12
FN7184.2 May 16, 2007
EL5197, EL5197A Applications Information
Product Description
The EL5197 is a fixed gain amplifier that offers a wide -3dB bandwidth of 200MHz and a low supply current of 4mA. The EL5197 works with supply voltages ranging from a single 5V to 10V and they are also capable of swinging to within 1V of either supply on the output. This combination of high bandwidth and low power, together with aggressive pricing make the EL5197 the ideal choice for many low-power/highbandwidth applications such as portable, handheld, or battery-powered equipment. For varying bandwidth and higher gains, consider the EL5191 with 1GHz on a 9mA supply current or the EL5193 with 300MHz on a 4mA supply current. Versions include single, dual, and triple amp packages with 5 Ld SOT-23, 16 Ld QSOP, and 8 Ld or 16 Ld SOIC outlines. temperature and process, external resistor should not be used to adjust the gain settings.
400
400 ININ+ +
FIGURE 1. AV = +2
400 400 ININ+ +
FIGURE 2. AV = -1
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Low impedance ground plane construction is essential. Surface mount components are recommended, but if leaded components are used, lead lengths should be as short as possible. The power supply pins must be well bypassed to reduce the risk of oscillation. The combination of a 4.7F tantalum capacitor in parallel with a 0.01F capacitor has been shown to work well when placed at each supply pin.
IN400 + IN+
400
FIGURE 3. AV = +1
Disable/Power-Down
The EL5197A amplifier can be disabled placing its output in a high impedance state. When disabled, the amplifier supply current is reduced to < 150A. The EL5197A is disabled when its CE pin is pulled up to within 1V of the positive supply. Similarly, the amplifier is enabled by floating or pulling its CE pin to at least 3V below the positive supply. For 5V supply, this means that an EL5197A amplifier will be enabled when CE is 2V or less, and disabled when CE is above 4V. Although the logic levels are not standard TTL, this choice of logic voltages allows the EL5197A to be enabled by tying CE to ground, even in 5V single supply applications. The CE pin can be driven from CMOS outputs.
Supply Voltage Range and Single-Supply Operation
The EL5197 has been designed to operate with supply voltages having a span of greater than or equal to 5V and less than 11V. In practical terms, this means that the EL5197 will operate on dual supplies ranging from 2.5V to 5V. With single-supply, the EL5197 will operate from 5V to 10V. As supply voltages continue to decrease, it becomes necessary to provide input and output voltage ranges that can get as close as possible to the supply voltages. The EL5197 has an input range which extends to within 2V of either supply. So, for example, on 5V supplies, the EL5197 has an input range which spans 3V. The output range of the EL5197 is also quite large, extending to within 1V of the supply rail. On a 5V supply, the output is therefore capable of swinging from -4V to +4V. Single-supply output range is larger because of the increased negative swing due to the
Gain Setting
The EL5197A is built with internal feedback and gain resistors. The internal feedback resistors have equal value; as a result, the amplifier can be configured into gain of +1, -1, and +2 without any external resistors. Figure 1 shows the amplifier in gain of +2 configuration. The gain error is 2% maximum. Figure 2 shows the amplifier in gain of -1 configuration. For gain of +1, IN+ and IN- should be connected together as shown in Figure 3. This configuration avoids the effects of any parasitic capacitance on the IN- pin. Since the internal feedback and gain resistors change with
13
FN7184.2 May 16, 2007
EL5197, EL5197A
external pull-down resistor to ground. Figure 4 shows an ACcoupled, gain of +2, +5V single supply circuit configuration.
400
Current Limiting
The EL5197 has no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device.
+5
Power Dissipation
With the high output drive capability of the EL5197, it is possible to exceed the 125C Absolute Maximum junction temperature under certain very high load current conditions. Generally speaking when RL falls below about 25, it is important to calculate the maximum junction temperature (TJMAX) for the application to determine if power supply voltages, load conditions, or package type need to be modified for the EL5197 to remain in the safe operating area. These parameters are calculated as follows:
T JMAX = T MAX + ( JA x n x PD MAX ) FIGURE 4.
400 +5 0.1F 0.1F VIN 1k 1k + VOUT
Video Performance
For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150, because of the change in output current with DC level. Previously, good differential gain could only be achieved by running high idle currents through the output transistors (to reduce variations in output impedance.) These currents were typically comparable to the entire 4mA supply current of each EL5197 amplifier. Special circuitry has been incorporated in the EL5197 to reduce the variation of output impedance with current output. This results in dG and dP specifications of 0.03% and 0.04, while driving 150 at a gain of 2. Video performance has also been measured with a 500 load at a gain of +1. Under these conditions, the EL5197 has dG and dP specifications of 0.03% and 0.04, respectively.
where: TMAX = Maximum ambient temperature JA = Thermal resistance of the package n = Number of amplifiers in the package PDMAX = Maximum power dissipation of each amplifier in the package PDMAX for each amplifier can be calculated as follows:
V OUTMAX PD MAX = ( 2 x V S x I SMAX ) + ( V S - V OUTMAX ) x --------------------------R
L
where: VS = Supply voltage ISMAX = Maximum supply current of 1A VOUTMAX = Maximum output voltage (required) RL = Load resistance
Output Drive Capability
In spite of its low 4mA of supply current, the EL5197 is capable of providing a minimum of 95mA of output current with a minimum of 95mA of output drive.
Driving Cables and Capacitive Loads
When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, the back-termination series resistor will decouple the EL5197 from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. In these applications, a small series resistor (usually between 5 and 50) can be placed in series with the output to eliminate most peaking.
14
FN7184.2 May 16, 2007
EL5197, EL5197A Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
15
FN7184.2 May 16, 2007
EL5197, EL5197A SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES:
E1 2 3
E
A2 b c
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
D E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only).
(L1)
H
6. SOT23-5 version has no center lead (shown as a dashed line).
A
GAUGE PLANE c L 0 +3 -0
0.25
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN7184.2 May 16, 2007

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